1. Field of the Invention
The present invention relates to a clock generating circuit used in a semiconductor memory device, and particularly relates to a clock generating circuit which generates an internal clock signal synchronized with an externally applied clock signal by means of a digital DLL (Delay Locked Loop) as well as a semiconductor memory device provided with the same.
2. Description of the Background Art
For generating a clock signal within a semiconductor memory device, such an technique has been known that a clock generating circuit (which will also be referred to merely as a xe2x80x9cDLL circuitxe2x80x9d hereinafter) employing the digital DLL is used for delaying a phase of an externally applied clock signal, and thereby the internal clock signal synchronized with the external clock is generated. This technique is particularly important in an SDRAM (Synchronous Dynamic Random Access Memory).
FIG. 12 is a block diagram showing a structure of a clock generating circuit 500 in the prior art employing the digital DLL.
Referring to FIG. 12, clock generating circuit 500 includes a delay circuit 510 which delays an input clock signal SIGIN of a cycle time Tcyc, a phase comparator circuit 520 which makes a comparison between phases of an output clock signal SIGOUT generated from delay circuit 510 and input clock signal SIGIN, and a delay control circuit 530 which controls the amount of delay of delay circuit 510 in accordance with the result of comparison of phase comparator circuit 520.
Delay circuit 510 is also called a xe2x80x9cdelay linexe2x80x9d and, for example, includes delay units 515-1-515-n each providing a delay amount td. In this case, delay control circuit 530 operates in response to the result of phase comparison of phase comparator circuit 520 to increase or decrease the number of delay units to be activated in delay circuit 510. In general, each of delay units 515-1-515-n in delay circuit 510 employs a semiconductor element circuit such as an inverter, which is formed of field-effect transistors.
As described above, the total delay amount provided by delay circuit 510 is controlled in accordance with the result of phase comparison so that the output clock signal SIGOUT is delayed by the amount equal to one cycle time Tcyc from input clock signal SIGIN, whereby it is possible to produce the clock signal having the phase coincident with that of the input clock signal. In the following description, the state where the phases of the input and output clock signals are coincident with each other will also be referred to as a xe2x80x9clocked statexe2x80x9d.
In general, the clock generating circuit in the prior art uses a Voltage Down Converter (which will also be referred to merely as a xe2x80x9cVDCxe2x80x9d hereinafter) for stabilizing a drive potential Vc of these delay units so that delay amount td of each delay unit is set to a constant value. Additionally, the number of delay units to be activated is controlled. Thereby, the synchronized state is ensured.
However, in a field-effect transistor such as an MOS transistor forming an inverter, a channel resistance has a temperature dependency. More specifically, the channel resistance value is small in a low temperature region, and is large in a high temperature region.
In accordance with this characteristic, the inverter formed of the MOS transistors delays the signal by a small amount in the low temperature region, and delays it by a large amount in the high temperature region. Accordingly, the delay unit provides delay amount td, which is variable depending on the temperature region, and more specifically, provides delay amount td, which is small in the low temperature region, and is large in the high temperature region, even if the delay unit has the constant structure.
FIG. 13 conceptually shows a problem relating to temperature conditions of a clock generating circuit 500 in the prior art.
Referring to FIG. 13, temperatures Tn and Tx correspond to an operation-ensured range of clock generating circuit 500. For example, the range between Tn and Tx corresponds to the operation specification temperature range of the semiconductor memory device provided with clock generating circuit 500. In general, Tn is about xe2x88x9240xc2x0 C., and Tx is about 120xc2x0 C.
The ordinate gives the total delay amount which can be provided by delay circuit 510 in clock generating circuit 500. After clock generating circuit 500 entered the locked state, the locked state must be maintained by adjusting the total delay amount of delay circuit 510 in clock generating circuit 500. Accordingly, the total delay amount which can be applied by entire delay circuit 510 determines the lock-allowing frequency range, i.e., the frequency range allowing locking in clock generating circuit 500.
In FIG. 13, delay amount DT0 corresponds to the case where delay circuit 510 applies the minimum delay amount at minimum specified temperature Tn. In this case, the minimum number of delay units are activated. Delay amount DT1 is a total delay amount in the case where the minimum number of delay units are activated at maximum specified temperature Tx.
Delay amount DT2 is applied in the case where all the delay units are activated at minimum specified temperature Tn, and is given by nxc2x7td in connection with the number and amount in FIG. 12. At the maximum specified temperature Tx, delay amount td per unit increases in accordance with increase in channel resistance caused by rise in temperature, and therefore the total delay amount, which is obtained by activating all the delay units, takes on a value of DT3 larger than DT2. Frequencies f0-f3 correspond to inverses of total delay amounts DT0-DT3, respectively, and establish a relationship of f3 less than f2 less than f1 less than f0.
The lock-allowing frequency range at maximum specified temperature Tx is between f 1and f3, but the lock-allowing frequency range at minimum specified temperature Tn is between f0 and f2, and therefore is significantly narrow. In a hatched region in FIG. 13, therefore, the total delay amount is not enough to synchronize the input and output clock signals with each other. As a result, only the range of f1-f2 forms the lock-allowing operation frequency range in the whole range according to the operation specifications relating to the temperature.
As described above, the lock-allowing frequency range changes to a large extent particularly on the low frequency side in accordance with variations in temperature conditions. Therefore, clock generating circuit 500 in the prior art must be provided with an appropriate number of delay units, which are required for ensuring the operation frequency range on the low frequency side with respect to the minimum specified temperature. This causes a problem of increase in layout area.
An object of the invention is to provide a clock generating circuit which can ensure a wide lock-allowing frequency range while requiring a small layout area.
Another object of the invention is to provide a semiconductor memory device provided with a clock generating circuit which generates an internal clock signal in synchronization with an external clock signal, and can ensure a wide lock-allowing frequency range while requiring a small layout area.
In summary, a clock generating circuit includes a delay circuit, a phase comparator circuit, a drive potential control circuit and a delay control circuit.
The delay circuit delays the input clock signal and outputs the delayed input clock signal. The delay circuit includes a plurality of delay units for delaying the input clock signal by a first delay amount obtained by multiplying a first unit delay amount by L (L: a natural number), and the first unit delay amount changes in accordance with a drive potential of the plurality of delay units. The phase comparator circuit makes a comparison between phases of the input clock signal and the output signal of the delay circuit. The drive potential control circuit controls the drive potential in response to a result of phase comparison of the phase comparator circuit. The delay control circuit controls L in response to the result of phase comparison.
According to another aspect, a clock generating circuit includes a delay circuit, a phase comparator circuit and a drive potential control circuit.
The delay circuit is supplied with a drive potential for operating to delay an input clock signal by a delay amount corresponding to the drive potential and output the delayed input clock signal. The phase comparator circuit makes a comparison between phases of the input clock signal and the output signal of the delay circuit. The drive potential control circuit controls the drive potential in response to the result of phase comparison of the phase comparator circuit.
According to still another aspect of the invention, a semiconductor memory device operating in synchronization with an external clock signal includes a memory cell array, a data terminal, a buffer circuit and a clock generating circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns. The data terminal inputs and outputs data for writing and reading with respect to the memory cell array. The buffer circuit executes data transmission between the memory cell array and the data terminal in response to an internal clock signal. The clock generating circuit generates the internal clock signal synchronized with the external clock signal.
The clock generating circuit includes a delay circuit for delaying the external clock signal to output the internal clock signal. The delay circuit has a plurality of delay units for delaying the external clock signal by a first delay amount obtained by multiplying a first unit delay amount by L (L: a natural number), and the first unit delay amount changes in accordance with a drive potential of the plurality of delay units. The clock generating circuit further includes a phase comparator circuit for making a comparison between phases of the external clock signal and the internal clock signal of the delay circuit, a drive potential control circuit for controlling the drive potential in response to the result of phase comparison of the phase comparator circuit, and a delay control circuit for controlling L in response to the result of phase comparison of the phase comparator circuit.
According to the invention described above, the following major advantages can be achieved. The delay amount of the delay circuit is changed also by reflecting the phase comparison result in the drive potential of the delay units. Therefore, the frequency range of the input clock signal, in which the synchronized state can be ensured, can be widened without increasing the number of the delay units. Accordingly, the layout of the clock generating circuit can be efficient.
Since the delay amount of the delay circuit is changed by reflecting the phase comparison result in the drive potential of the delay units, the frequency range of the input clock signal, in which the synchronized state can be ensured, can be widened on the lower frequency side without increasing the number of the delay units. Accordingly, the layout of the clock generating circuit can be efficient.
The internal clock synchronized with the external clock is generated by the clock generating circuit, in which the delay amount of the delay circuit can be changed also by reflecting the phase comparison result in the drive potential of the delay units. In the clock generating circuit, therefore, the frequency range of the external clock signal, in which the synchronized state can be ensured, can be widened without increasing the number of the delay units. Accordingly, the layout of the clock generating circuit can be efficient, and the layout area of the semiconductor memory device can be reduced.